Semiconductor-memory reading circuits perform a comparison between two currents (or voltages) to read the data stored in memory cells. A current (or voltage) of a memory cell selected for reading is compared with a reference current (or voltage). The reference currents (or voltages) for the reading circuits are typically generated with the use of reference memory cells which are structurally identical to the memory cells and are programmed to predetermined levels, typically during the testing of the individual memory device.
There is a need to provide memories with ever larger bandwidths and ever lower energy consumption per individual bit. This need is imposed by the ever higher performance of electronic systems. On the other hand, the time required to perform reading cannot be reduced indefinitely since it is limited by physical constraints such as the charging time of the word lines of the memory. To achieve a greater bandwidth, it is therefore necessary to perform several cell readings in parallel. To be able to perform several readings in parallel, it is necessary to increase the number of cell-reading circuits and of respective circuits for generating reference currents (or voltages). This results in a significant increase in the area and energy consumption of the memory device.
To limit the increase in area and consumption, attempts have been made to limit the number of circuits for generating reference currents (or voltages). The same reference signal (current or voltage) generated at one point of the device is thus supplied to several cell-reading circuits by bringing the reference signal (current or voltage) to the various points of the device at which the reading circuits are arranged. The limiting of the number of reference-signal generating circuits brings advantages both in terms of area and in terms of consumption, and also in terms of the time required to test the individual device, since the number of reference cells to be programmed to the desired levels is reduced.
However, since the reference signal has to travel considerable distances inside the device, a large parasitic capacitance associated with the reference-signal distribution lines degrades the reference signal. It is also necessary to add the capacitances of the input nodes of the various cell-reading circuits which the reference signal supplies. The time required for the reference signal to reach the predetermined steady value therefore increases and the bandwidth of the memory device is limited. Moreover, since the various cell-reading circuits are coupled capacitively to the reference signal, the intrinsic imbalances in their operation in the course of the reading of the respective memory cells selected may cause errors in the reading, particularly when they are reading memory cells with large margins (distances between thresholds) involving large current or voltage ranges which alter the value of the reference signal.